Modern integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. This is especially true of ICs that use field effect transistors (FETs), especially metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors or devices. Although the term “MOS” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term is also used to refer to any semiconductor device that includes a conductive gate electrode (whether metal or not) that is positioned over a gate insulator (whether oxide or other dielectric material) which, in turn, is positioned over a semiconductor surface. Accordingly, the terms metal-oxide-semiconductor and the abbreviations “MOS” and “MOSFET” are used herein even though such devices may not employ just metals or oxides but combinations of conductive materials, e.g., alloys, silicides, doped semiconductors, etc., instead of simple metals, and insulating materials other than silicon oxides (e.g., nitrides, oxy-nitrides, other oxides, mixtures of dielectric materials, organic dielectrics, etc.). Thus, as used hereon the terms MOS and MOSFET are intended to include these and other variations.
A typical MOS transistor includes a gate as a control electrode and spaced-apart source and drain regions between which a current can flow. A control voltage applied to the gate adjusts the flow of current through a controllable conductive channel between the source and drain. Because the gate dielectric on most MOSFETS is relatively thin, it can be easily damaged if excess voltage appears on the gate terminal. It is well known that electrostatic discharge from handling MOS ICs is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input and/or other terminals of such MOSFETS and IC's employing MOSFETS. FIG. 1 is a simplified schematic diagram of circuit 20 wherein ESD clamp 21 is placed between input-output (I/O) terminal 22 and ground or common terminal 23 of an IC to protect other devices on the chip, that is, “circuit core” 24 coupled to the I/O and common terminals 22, 23. FIG. 2 is a simplified schematic diagram illustrating internal components of ESD clamp 21, utilizing bipolar transistor 25, having emitter 26, collector 27, base 28, resistance 29 and Zener diode 30 having terminals 301, 302. When the voltage across terminals 22, 23 rises beyond a predetermined limit, Zener diode 30 turns on, thereby switching bipolar transistor 25 into conduction and clamping the voltage across terminals 22, 23 at a level below that capable of damaging circuit core 24.
FIG. 3 shows simplified cross-sectional view 32 of ESD clamp 31 implementing ESD clamp 21 of FIGS. 1-2 in semiconductor substrate 37, according to the prior art. FIG. 4 shows simplified plan view 33 of ESD clamp 31 of FIG. 3. FIGS. 3 and 4 should be considered together. ESD clamp 31 comprises N-type buried layer (NBL) 34 above which lies P-type layer or region 36. P-well region 38 extends from surface 35 into P region 36. N-type sinkers 40 extend from surface 35 to make ohmic electrical contact to NBL 34. N+ regions 42 make ohmic contact to N-type sinkers 40. P+ regions 43 and 45 make ohmic contact to P-well 38. P-well 38 serves as the base of transistor 25 (see FIG. 2). N+ region 44 serves as the emitter of transistor 25. P+ region 45 serves as anode 301 of Zener diode 30 (see FIG. 2) whose cathode 302 is provided by N-type sinker 40 and N+ contact 42. Zener space charge region (abbreviated as “ZSC”) 39 is located between P+ region 45, and N-sinker 40 with N+ contact 42. Anode terminal 22 of ESD clamp 31 is coupled to N+ region 42 and cathode terminal 23 of ESD clamp 31 is coupled to N+ region 44.
While such prior art devices are widely used as ESD clamps, they suffer from a number of limitations. Typical limitations are illustrated, for example, in FIG. 5. FIG. 5 shows plot 46 of the current (in milli-amps) between terminals 22, 23 of ESD clamp 31 as a function of the voltage (in volts) across terminals 22, 23 for nominally identical clamps, 311, 312, 313, 314, etc., (collectively 31) located in different regions and orientations of the same IC, and fabricated at the same time using the same mask set. ESD clamps 31 are intended to clamp the terminal voltage at about 10-12 volts. However, it is observed that some of the ESD clamps (e.g., ESD 311, 312) turn on at about 10-11 volts while others on the same chip (e.g., 314) do not turn on until the terminal voltage reaches 17-19 volts. This is observed even though ESD clamps 311, 312, 313, 314, etc., are manufactured at the same time using the same mask set on the same substrate, and would be expected to exhibit nearly identical properties no matter where they are located on the IC chip. This variability is undesirable since it exposes some I/O terminals and their associated circuit cores to significantly larger ESD voltages than other parts of the overall IC.
Accordingly, there is an ongoing need to provide improved ESD clamps, especially ESD clamps that operate at more consistent voltages independent of their location in a particular IC. Further, it is desirable that the improved ESD clamps be obtainable without significant modification of the manufacturing process used for forming the clamps and their associated circuit core of the IC. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.